The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down however has also increased the complexity of processing and manufacturing ICs and, thus, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as IC technologies are continually progressing to smaller technology nodes simply scaling down similar designs used at larger feature sizes often results in poorly shaped device features due to the constraints of the available lithography tools. Typically insufficient fidelity between a device feature formed on a substrate as compared to the as-drawn feature provided on a photomask is a common issue. Resolution enhancement techniques (RET) such as optical proximity correction (OPC) have been employed to improve this fidelity. However, performing such rule or model based corrections on an entire design to reach a desired fidelity can be time and resource consuming. Lithography tool advances themselves, such as immersion lithography and other enhancements steppers and scanners, have also been developed. However, the efficiency and effectiveness of these enhancements also presents a challenge. Therefore, while existing methods for improving IC design and manufacturing have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.